1. Field of the Invention
The present invention relates to a semiconductor memory device and method of fabricating the same, and in particular, to a ferroelectric memory device and method of manufacturing a ferroelectric.
2. Background of the Related Art
As semiconductor device integration increases, the capacitor area per unit cell is decreased, which in turn reduces the capacitance. The thickness of a dielectric film has been gradually decreased to compensate for the reduction of the capacitance. However, the decrease in the thickness of the dielectric film causes a high leakage current problem, which lowers the reliability of the semiconductor device.
To solve the high leakage current problem, a very complicated surface undulation can be created, which increases the effective area of a capacitor. However, the surface undulation technique makes photolithography difficult and raises the manufacturing costs, which is disadvantageous to a semiconductor device of high integration.
Research devoted to planarization, in contrast to the surface undulation technique that increased the capacitance, proposed a technique employing a material of high permittivity as a dielectric film. A capacitor made of the high dielectric film has several advantages, however, the scope of its use is limited since its actual permittivity is not very high when the increased integration of semiconductor devices is taken into consideration. Perovskite, a ferroelectric whose crystal structure is ideally cubic, was investigated as a material to be used in a semiconductor device. A ferroelectric is a crystalline substance displaying ferroelectricity (i.e., spontaneous electric polarization) when heated below its Curie temperature without applying electric field. Ferroelectrics include PZT (Pb (Zr, Ti) O.sub.3), PLZT ((Pb, La)(Zr, Ti)O.sub.3), BST ((Ba, Sr)TiO.sub.3), BaTiO.sub.3, and SrTiO.sub.3.
Such ferroelectrics react on silicon or silicide, and its surface is exposed in a strong acid atmosphere, thus causing various problems such as oxidization of electrodes. Suitable materials and structures for electrodes are being investigated to solve those problems. Since the ferroelectric is an oxide, electrodes should be made of conductive materials that are not easily oxidized. Accordingly, platinum (Pt) is generally used as an electrode. FeRAM, a non-volatile memory device, is identical to dynamic random access memory (DRAM) in structure, but employs a ferroelectric as a capacitor. In contrast, DRAM (volatile memory device) uses a paraelectric material as a capacitor. FeRAM assures a low-voltage and high-speed performance, and does not require periodic refresh to prevent loss of information during standby intervals.
FIG. 1 illustrates a related hysteresis loop, and FIG. 2 graphically depicts charge-voltage characteristics of a related art ferroelectric. As shown in FIG. 1, the relation between polarization and applied electric field (P-E) of a ferroelectric is not shown by a straight line on a graph but is displayed on a hysteresis loop. According to the hysteresis loop, a direction of the spontaneous electric polarization may be inverted by changing a direction of the applied voltage. In FIG. 1, P is flux density, E is an applied electric field and Pr is retentivity.
As shown in FIG. 2, a capacitor for a feRAM is made of a ferroelectric that exhibits electrical properties analogous to certain magnetic properties, not paraelectric. The ferroelectric has two kinds of electric charges, opposite to each other in state, without application of voltage. At this point, "1" and "0" respectively denote a negative charge and a positive charge, and Q1, Q0, Qr, and Qs respectively designate a quantity of charge displacement, a quantity of displaced charges, a quantity of retentivity and a quantity of saturated charges.
FIG. 3 illustrates a circuit diagram of related art 1 transistor/1 capacitor structure, and FIG. 4 illustrates a timing diagram of FIG. 3. FIG. 5 graphically depicts charge-voltage characteristics of a related art ferroelectric. As shown in FIG. 3, the related 1 transistor/1 capacitor structure includes a word line W/L connected to a gate of a memory cell 1 in one direction, a bit line B/L that is perpendicular to the word line W/L connected to a drain of the memory cell 1 and a ferroelectric capacitor C connected to a source of the memory cell 1. A data line D/L that is parallel to the word line W/L is connected to the ferroelectric capacitor C and a sense amplifier SA is connected to the bit line B/L for sensing data. A reference cell 2 is also connected to any one of input terminals of the sense amplifier SA for generating a reference voltage.
The operation of the related art semiconductor memory device will now be described. A capacitor of the reference cell 2 is half the size of the capacitor of the memory cell 1 and a driving voltage applied to the reference cell 2 is the same as the memory cell 1. As shown in FIGS. 3, 4 and 5, a high-level signal is applied to the word line W/L to turn on a transistor Tr for storing "1" in capacitor C of memory cell 1. A pulse is applied to bit line B/L to make ferroelectric capacitor C of each of the memory cell 1 and the reference cell 2 "1".
To read out "1", a high-level signal is applied to word line W/L to turn on transistor Tr. A pulse applied to data line D/L inverts ferroelectric capacitor C of memory cell 1. The sense amplifier SA compares Q1 (e.g., Q1 equals Qs+Qr), which is discharged to the bit line B/L, to a reference charge Qref of the reference cell 2. If Q1 of the memory cell 1 is larger than Qref of reference cell 2, the sense amplifier SA latches Q1 to produce a high-level signal to bit line B/L. "1" is restored through the above steps. At this point, Qref of reference cell 2 equals to Qr of memory cell 1.
To store "0" in the capacitor C of the memory cell 1, a high-level signal is applied to the word line W/L to turn on the transistor Tr, and a pulse is applied to the data line D/L to make the ferroelectric capacitor C of each of the memory cell 1 and the reference cell 2 "0".
To read out "0", a pulse is applied to data line D/L not to invert ferroelectric capacitor C of memory cell 1. The sense amplifier SA compares Q0 (e.g., Q0 equals Qs-Qr), which is discharged to the bit line B/L, with the reference charge Qref of reference cell 2. If Q0 of the memory cell 1 is smaller than Qref of the reference cell 2, the sense amplifier SA latches a low-level signal not to produce a high-level signal to bit line B/L so that data remains "0". At this point, if Qref of reference cell 2 is larger than Q0 and smaller than Q1, "1" can be distinguished from "0", and a sensing margin becomes maximum. That is, since Q1-Q0 equals 2Qr, it is preferable that Qref equals Qr.
As described above, the related art memory device has various problems. When reading data out of selected memory cells each connected to bit lines, corresponding reference cells are selected and generate a reference charge by polarization/inversion, which causes fatigue of the reference cells. In addition, when the reference potential produced from the reference cells is decreased to an amount smaller than the quantity of displaced charges, "1" cannot be distinguished from "0".